LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dec_pkg.all;
entity v1col is port (
	        clk :in  std_ulogic;
                wb_clk :in  std_ulogic;
	        wb_en  : in std_ulogic;
	        sel8 : in std_ulogic_vector(3 downto 0);
                wb_addr :in std_ulogic_vector(7 downto 0);
                wb_data :in std_ulogic_vector(7 downto 0); 
                enable : in std_ulogic;
                state1 : in std_ulogic;
                vup_length : in frame_length;
                b_len : in block_length;
                cup16_end :in std_ulogic;
                vup_enable : in std_ulogic;
                count_vr : in std_ulogic_vector(6 downto 0);
		e1 : in word32;
	        e2 : in word32;
		e3 : in word32;
                e4 : in word32;
	        e5 : in word32;
	        e6 : in word32;
	        e7 : in word32;
	        e8 : in word32;
	        q1 : out word32;
	        q2 : out word32;
	        q3 : out word32;
	        q4 : out word32;
	        q5 : out word32;
	        q6 : out word32;
	        q7 : out word32;
	        q8 : out word32;
	        b  : out word32);
end entity ;
architecture rtl of v1col is
	component vup_line1 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
    frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
    llrq: out std_ulogic_vector(31 downto 0);
    b_len: in integer range 50 to 512
 --   vup_outflag: out std_ulogic
    );
end component;

component vup_line2 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
    frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
    b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
   -- vup_outflag: out std_ulogic
    );
end component;

component vup_line3 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
    frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
   b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
    --vup_outflag: out std_ulogic
    );
end component;

component vup_line4 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
    frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
    b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
  --  vup_outflag: out std_logic
    );
end component;

component vup_line5 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
       frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
        b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
  --  vup_outflag: out std_logic
    );
end component;

component vup_line6 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
        frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
        b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
   -- vup_outflag: out std_ulogic
    );
end component;

component vup_line7 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
        frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
        b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
   -- vup_outflag: out std_ulogic
    );
end component;

component vup_line8 is
port(
    clk: in std_ulogic;
    flag: in std_ulogic;
    flag2: in std_ulogic;
    flgout2: in std_ulogic;
    frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    e1: in std_ulogic_vector(31 downto 0);
    e2: in std_ulogic_vector(31 downto 0);
    e3: in std_ulogic_vector(31 downto 0);
    e4: in std_ulogic_vector(31 downto 0);
    e5: in std_ulogic_vector(31 downto 0);
    e6: in std_ulogic_vector(31 downto 0);
    e7: in std_ulogic_vector(31 downto 0);
        b_len: in integer range 50 to 512;
    llrq: out std_ulogic_vector(31 downto 0)
   -- vup_outflag: out std_ulogic
    );
end component;
component LVT_CLKLAHAQVHSV4   is 
  port (
     Q : out std_ulogic;
     E : in std_ulogic;
     TE : in std_ulogic;
     CK : in std_ulogic
    );
  end component ;
component judge is
port(
    clk: in std_ulogic;
    inflag: in std_ulogic;
    frame: in integer range 0 to 4096;
    addr1: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr2: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr3: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr4: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr5: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr6: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr7: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    addr8: in std_ulogic_vector(15 downto 0); --the row position scan from colmum of each sub-matrix
    b1: in std_ulogic_vector(31 downto 0);
    b2: in std_ulogic_vector(31 downto 0);
    b3: in std_ulogic_vector(31 downto 0);
    b4: in std_ulogic_vector(31 downto 0);
    b5: in std_ulogic_vector(31 downto 0);
    b6: in std_ulogic_vector(31 downto 0);
    b7: in std_ulogic_vector(31 downto 0);
    b8: in std_ulogic_vector(31 downto 0); 
   -- judge_flag: out std_ulogic;
    b_len: in integer range 50 to 512;
  --  b :out std_ulogic;
    softbits: out word32
    );
end component;
 
component rf128x16mux2 is 
  port ( 
  QA: out std_logic_vector(15 downto 0);
  CLKA: in std_logic;
  CENA: in std_logic;
  AA: in std_logic_vector(6 downto 0);  
  CLKB: in std_logic;
  CENB: in std_logic;
  BWENB: in std_logic_vector(15 downto 0);
  AB: in std_logic_vector(6 downto 0);
  DB: in std_logic_vector(15 downto 0)
  );
end component;


signal en : std_ulogic_vector(7 downto 0);
signal vupads1,vupads2,vupads3,vupads4,vupads5,vupads6,vupads7,vupads8:std_ulogic_vector(15 downto 0);
signal cal_len : frame_length;
signal temp :std_ulogic_vector(4 downto 0);
signal gclk :std_ulogic;
signal ab : std_logic_vector(6 downto 0);
signal bwenb : std_logic_vector(15 downto 0);
signal db : std_logic_vector(15 downto 0);
signal cena : std_ulogic;
signal aa : std_logic_vector(6 downto 0); 
signal qa1,qa2,qa3,qa4,qa5,qa6,qa7,qa8 :std_logic_vector(15 downto 0);
--signal x : integer ;
begin 
  vupads1 <= std_ulogic_vector(qa1);
  vupads2 <= std_ulogic_vector(qa2);
  vupads3 <= std_ulogic_vector(qa3);
  vupads4 <= std_ulogic_vector(qa4);
  vupads5 <= std_ulogic_vector(qa5);
  vupads6 <= std_ulogic_vector(qa6);
  vupads7 <= std_ulogic_vector(qa7);
  vupads8 <= std_ulogic_vector(qa8);
    ab <= std_logic_vector(wb_addr(7 downto 1));
    temp <= sel8 & wb_en ;
    --- ram bit write enable 
    bwenb(15 downto 8) <= (not wb_addr(0)) &  (not wb_addr(0)) & (not wb_addr(0)) & (not wb_addr(0)) & (not wb_addr(0)) & (not wb_addr(0)) & (not wb_addr(0)) & (not wb_addr(0));
    bwenb(7 downto 0) <= wb_addr(0) & wb_addr(0) &  wb_addr(0) & wb_addr(0) & wb_addr(0) & wb_addr(0)& wb_addr(0) & wb_addr(0);
    cena <= not vup_enable;
    aa <= std_logic_vector(count_vr);
    process(wb_addr(0)) 
      begin 
        if wb_addr(0) = '0' then
             db <=  "00000000" & std_logic_vector(wb_data); 
           else 
             db <= std_logic_vector(wb_data) & "00000000";
           end if ;
         end process ; 
     process (temp,enable)
     begin 
	      if enable = '1' then 
	      case temp is 
		    when "10001" =>  en <= "11111110"; 
		    when "10011" =>  en <= "11111101";
		    when "10101" =>  en <= "11111011";
		    when "10111" =>  en <= "11110111";
		    when "11001" =>  en <= "11101111";
		    when "11011" =>  en <= "11011111";
		    when "11101" =>  en <= "10111111";
		    when "11111" =>  en <= "01111111";
		    when others => en <= (others => '1');
		      end case ;
		      else 
		        en <= (others => '1');
		        end if;
	    
      
    end process ;
	    
      
   
     process(clk)
       begin 
       if clk'event and clk = '1' then 
         if state1 = '0' then 
           cal_len <= vup_length;
         end if;
       end if;
     end process;
	 g: LVT_CLKLAHAQVHSV4   port map(
                  CK => clk ,
                  Q =>  gclk,
                  E => vup_enable,
                  TE => '0'
                 );
    
        vup_rag1 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(0) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa1
                                     );
        vup_rag2 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(1) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa2
                                     );
        vup_rag3 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(2) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa3
                                     );
        vup_rag4 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(3) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa4
                                     );
        vup_rag5 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(4) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa5
                                     );
        vup_rag6 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(5) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa6
                                     );
        vup_rag7 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(6) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa7
                                     );
        vup_rag8 : rf128x16mux2 port map(CLKB => wb_clk,
                                         CENB => en(7) ,
                                         AB => ab,
                                         BWENB => bwenb ,
                                         DB => db,
                                         CLKA => clk ,
                                         CENA => cena ,
                                         AA =>  aa,
                                         QA => qa8
                                     );
                        


v11:vup_line1 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads2,addr2=>vupads3,addr3=>vupads4,addr4=>vupads5,addr5=>vupads6,addr6=>vupads7,addr7=>vupads8,e1=>e2,e2=>e3,e3=>e4,e4=>e5,e5=>e6,e6=>e7,e7=>e8,b_len =>  b_len ,llrq=>q1);
v21:vup_line2 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads3,addr3=>vupads4,addr4=>vupads5,addr5=>vupads6,addr6=>vupads7,addr7=>vupads8,e1=>e1,e2=>e3,e3=>e4,e4=>e5,e5=>e6,e6=>e7,e7=>e8,b_len =>  b_len ,llrq=>q2);
v31:vup_line3 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads4,addr4=>vupads5,addr5=>vupads6,addr6=>vupads7,addr7=>vupads8,e1=>e1,e2=>e2,e3=>e4,e4=>e5,e5=>e6,e6=>e7,e7=>e8,b_len =>  b_len ,llrq=>q3);
v41:vup_line4 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads3,addr4=>vupads5,addr5=>vupads6,addr6=>vupads7,addr7=>vupads8,e1=>e1,e2=>e2,e3=>e3,e4=>e5,e5=>e6,e6=>e7,e7=>e8,b_len =>  b_len ,llrq=>q4);
v51:vup_line5 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads3,addr4=>vupads4,addr5=>vupads6,addr6=>vupads7,addr7=>vupads8,e1=>e1,e2=>e2,e3=>e3,e4=>e4,e5=>e6,e6=>e7,e7=>e8,b_len =>  b_len ,llrq=>q5);
v61:vup_line6 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads3,addr4=>vupads4,addr5=>vupads5,addr6=>vupads7,addr7=>vupads8,e1=>e1,e2=>e2,e3=>e3,e4=>e4,e5=>e5,e6=>e7,e7=>e8,b_len =>  b_len ,llrq=>q6);
v71:vup_line7 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads3,addr4=>vupads4,addr5=>vupads5,addr6=>vupads6,addr7=>vupads8,e1=>e1,e2=>e2,e3=>e3,e4=>e4,e5=>e5,e6=>e6,e7=>e8,b_len =>  b_len ,llrq=>q7);
v81:vup_line8 port map(flag=>'1',clk => gclk ,flag2=>vup_enable,flgout2=>cup16_end,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads3,addr4=>vupads4,addr5=>vupads5,addr6=>vupads6,addr7=>vupads7,e1=>e1,e2=>e2,e3=>e3,e4=>e4,e5=>e5,e6=>e6,e7=>e7,b_len =>  b_len ,llrq=>q8);


j1:judge port map(inflag=>cup16_end,clk => gclk ,frame=>cal_len,addr1=>vupads1,addr2=>vupads2,addr3=>vupads3,addr4=>vupads4,addr5=>vupads5,addr6=>vupads6,addr7=>vupads7,addr8=>vupads8,b1=>e1,b2=>e2,b3=>e3,b4=>e4,b5=>e5,b6=>e6,b7=>e7,b8=>e8,softbits=>b,b_len => b_len );

end rtl ;
	
    
  
